By Daniel J. Sorin, Mark D. Hill, David A. Wood
Many smooth desktops and such a lot multicore chips (chip multiprocessors) aid shared reminiscence in undefined. In a shared reminiscence approach, all the processor cores might learn and write to a unmarried shared tackle area. For a shared reminiscence computer, the reminiscence consistency version defines the architecturally noticeable habit of its reminiscence procedure. Consistency definitions supply principles approximately a lot and shops (or reminiscence reads and writes) and the way they act upon reminiscence. As a part of aiding a reminiscence consistency version, many machines additionally supply cache coherence protocols that make sure that a number of cached copies of information are saved updated. The aim of this primer is to supply readers with a uncomplicated knowing of consistency and coherence. This knowing contains either the problems that has to be solved in addition to a number of strategies. We current either highlevel strategies in addition to particular, concrete examples from real-world platforms. desk of Contents: Preface / advent to Consistency and Coherence / Coherence fundamentals / reminiscence Consistency Motivation and Sequential Consistency / overall shop Order and the x86 reminiscence version / cozy reminiscence Consistency / Coherence Protocols / Snooping Coherence Protocols / listing Coherence Protocols / complex issues in Coherence / writer Biographies
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Additional resources for A Primer on Memory Consistency and Cache Coherence
4] presented two techniques for performing this check. First, after the core speculatively executes L2, but before it commits L2, the core could check that the speculatively accessed block has not left the cache. So long as the block remains in the cache, its value could not have changed Memory Consistency Motivation and Sequential Consistency 31 between the load’s execution and its commit. To perform this check, the core tracks the address loaded by L2 and compares it to blocks evicted and to incoming coherence requests.
Figure 4-1 (the same as Figure 3-1 in the previous chapter) illustrates the execution of this program. 2’s Program.
The memory system can respond to a load or store to block B if it has B with appropriate coherence permissions (state M or S 28 A Primer on Memory Consistency and Cache Coherence C1 Cn C2 Each core Ci seeks to do its next memory access in its program order