An ASIC Low Power Primer: Analysis, Techniques and by Rakesh Chadha

By Rakesh Chadha

This publication presents a useful primer at the strategies used in the layout of low energy electronic semiconductor units. Readers will enjoy the hands-on strategy which starts off shape the ground-up, explaining with easy examples what strength is, the way it is measured and the way it affects at the layout technique of application-specific built-in circuits (ASICs). The authors use either the Unified energy layout (UPF) and customary energy structure (CPF) to explain intimately the facility rationale for an ASIC after which consultant readers via a number of architectural and implementation thoughts that may aid meet the facility rationale. From studying method energy intake, to options that may be hired in a low energy layout, to an in depth description of 2 exchange criteria for taking pictures the facility directives at a number of levels of the layout, this publication is full of details that may provide ASIC designers a aggressive side in low-power design.

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1. 913mW (with 66ohm termination to VDDQ/2) Note that the above computation is for power dissipated within the IO buffer; there is additional power (supplied by VDDQ of the IO buffer) which is dissipated in the 66 ohm termination resistor. 2. The table illustrates that the power sourced by the VDDQ of the IO buffer is a different computation from the power dissipated within the IO buffer. Just like in the case of analog macros, the power description in the Liberty models is often not adequate for accurate power analysis in presence of resistive termination.

The back bias reduces the leakage contribution significantly while retaining the contents of the memory. This method of adding back bias to the core array may be referred to as deep sleep mode by some memory providers. Either or both of the methods can be utilized for leakage reduction. The key is that these methods can only be employed when the memory macro access is not required for a significant duration to justify the savings. After the design sets the control signals for placing the memory macro in the light sleep or the deep sleep mode, there is certain delay before the leakage reductions for the light sleep or the deep sleep mode are achieved.

Similar to the case described in previous subsection, the power sourced by the VDDQ supply of the IO buffer is an entirely different computation from the above. 4. Similar to the case described in previous subsection, the power dissipated in the IO is different from the power sourced by the VDDQ supply of the IO buffer. Similar to the output mode, the power description in the Liberty models is normally not adequate for accurate power analysis in input mode also. The dissipated power can be computed for steady state condition (output high or low) based upon the power supply VDDQ, input termination resistance, and the output drive impedance of the driver.

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