Analog Circuit Design for Process Variation-Resilient by Marvin Onabajo

By Marvin Onabajo

This booklet describes a number of strategies to deal with variation-related layout demanding situations for analog blocks in mixed-signal systems-on-chip. The equipment provided are effects from fresh study works related to receiver front-end circuits, baseband clear out linearization, and information conversion. those circuit-level thoughts are defined, with their relationships to rising system-level calibration ways, to music the performances of analog circuits with electronic tips or keep an eye on. assurance additionally contains a technique to make the most of on-chip temperature sensors to degree the sign strength and linearity features of analog/RF circuits, as established through attempt chip measurements.

  • Describes quite a few variation-tolerant analog circuit layout examples, together with from RF front-ends, high-performance ADCs and baseband filters;
  • Includes integrated checking out concepts, associated with present business trends;
  • Balances digitally-assisted functionality tuning with analog functionality tuning and mismatch relief approaches;
  • Describes theoretical recommendations in addition to experimental effects for try chips designed with variation-aware techniques.

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131–136 24. A. -L. Hussien, J. Silva-Martinez, E. Sánchez-Sinencio, An integrated frequency response characterization system with a digital interface for analog testing. IEEE J Solid-State Circuits 41(10), 2301–2313 (2006) 25. J. M. Ramzan, Built-in loopback test for IC RF transceivers. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(6), 933–946 (2010) 26. M. Onabajo, J. Silva-Martinez, F. Fernandez, E. Sánchez-Sinencio, An on-chip loopback block for RF transceiver built-in test. IEEE Trans.

21(4), 585–591 (2008) 7. A. Zivkovic, F. van der Heyden, G. Gronthoud, F. de Jong, Analog test bus infrastructure for RF/AMS modules in core-based design, in Proceedings of 13th European Test Symposium, May 2008, pp. 27–32 28 2 Process Variation Challenges and Solutions Approaches 8. K. Agarwal, J. Hayes, S. Nassif, Fast characterization of threshold voltage fluctuation in MOS devices. IEEE Trans. Semicond Manuf. 21(4), 526–533 (2008) 9. F. Glas, Digital I/Q imbalance compensation in a low-IF receiver, in Proceedings of IEEE Global Telecommunications Conference (GLOBECOM), vol.

Inon-lin{Vin/2}/Gm] = Vin/2 - inon-lin{Vin/2}/Gm. Under ideal conditions, the distortion generated in the auxiliary path, -inon-lin{Vin/2}, cancels out the distortion in the main voltage-to-current conversion. In practice, distortion components caused by nonlinearities at the output of the auxiliary OTA and high-frequency effects introduce some finite uncancelled distortion. 2 Attenuation-Predistortion Linearization Methodology 35 represents the lumped output capacitance of the auxiliary OTA, input capacitance of the main OTA, and layout parasitics.

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