Analog Integrated Circuit Design Automation: Placement, by Ricardo Martins, Nuno Lourenço, Nuno Horta

By Ricardo Martins, Nuno Lourenço, Nuno Horta

This e-book introduces readers to quite a few instruments for analog format layout automation. After discussing the location and routing challenge in digital layout automation (EDA), the authors assessment quite a few computerized structure iteration instruments, in addition to the latest advances in analog layout-aware circuit sizing. The dialogue comprises various equipment for automated placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The suggestions and algorithms of all of the modules are completely defined, permitting readers to breed the methodologies, enhance the standard in their designs, or use them as place to begin for a brand new instrument. all of the tools defined are utilized to sensible examples for a 130nm layout approach, in addition to placement and routing benchmark sets.

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ALADIN [52, 53] also allow designers to integrate their knowledge into the generation process. While ALG [51] uses the same knowledge-based principle, allowing the designer to interact with the tool in different phases but introducing a higher level of abstraction, leaving to the discretion of the designer if the final layout is obtained almost full automatically or by designer directives. In LAYGEN II [85, 86] a deterministic template-based placement over a B*-tree is performed, and 26 2 State-of-the-Art on Analog Layout Automation unlike previous approaches, a fully evolutionary approach is used to optimize the routing of any provided terminal-to-terminal connectivity.

5) is outdated for today’s integration technologies, the principles that the combined effects of current-density and temperature are responsible for the gradual degradation of the interconnect is still valid. 3 Electromigration-Aware Approaches Handling currents manually in analog circuits is an iterative and time-consuming process. Electromigration is an emergent topic [60, 61], the works addressing this problem focus essentially on how to deal with the multitude of current-densities observed in AMS circuits, and, how to assign and expand the widths of those interconnects accordingly in the routing step of the layout generation.

A detailed state-of-the-art on the pathfinding algorithms and analog layout routing difficulties can be found in the Chapter Routing Analog Circuits by Dündar and Unutulmaz of [1]. 2 Electromigration and IR-Drop AMS ICs suffer from diverse non-idealities that became increasingly more relevant with the reduction of the circuit sizes in the last years, and may cause catastrophic circuit failures. These non-idealities must be taken into account during the circuit design in order to mitigate their effect on the product reliability [56].

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