Debug Automation from Pre-Silicon to Post-Silicon by Mehdi Dehbashi, Görschwin Fey

By Mehdi Dehbashi, Görschwin Fey

This e-book describes computerized debugging techniques for the insects and the faults which seem in numerous abstraction degrees of a method. The authors hire a transaction-based debug method of platforms on the transaction-level, saying the proper relation of transactions. the automatic debug technique for layout insects unearths the capability fault applicants at RTL and gate-level of a circuit. Debug options for common sense insects and synchronization insects are verified, permitting readers to localize the main tricky insects. Debug automation for electric faults (delay faults)finds the doubtless failing speedpaths in a circuit at gate-level. a number of the debug ways defined in attaining excessive prognosis accuracy and decrease the debugging time, shortening the IC improvement cycle and lengthening the productiveness of designers.

  • Describes a unified framework for debug automation used at either pre-silicon and post-silicon stages;
  • Provides techniques for debug automation of a method at assorted degrees of abstraction, i.e., chip, gate-level, RTL and transaction level;
  • Includes suggestions for debug automation of layout insects and electric faults, in addition to an infrastructure to debug NoC-based multiprocessor SoCs.

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Extra info for Debug Automation from Pre-Silicon to Post-Silicon

Example text

The gates along the sensitized paths are the potential places on which the fault may be located. When there are multiple counterexamples and in each counterexample all faults are sensitized, the sensitized paths of counterexamples have common gates which define their intersection. Because the sensitized paths are derived from the faulty components. In this case, the gates on the intersected sensitized paths are potential components of fault candidates which propagate the error through different paths.

C) Sequential debugging stimuli create the erroneous output value. In the example of Fig. 5c, the length of counterexamples is two time steps. The correction block is added as in the combinational case and usually the same abnormal predicate is used for the same gate in all time steps and for all counterexamples. The set of the states of the circuit (flipflops) is denoted by S . An index is used to show the time step of the states. The case in which one component in the circuit is faulty is called single fault.

12. First the algorithm searches for the paths including a minimum number of Xs on the fault candidates (lines 10–15). When the convergence of L and the number of fault candidates is reached, the first step of LMBA is finished. Thus, the second step of LMBA starts. Now, the local branches of all fault candidates are activated (line 19–23) and the new counterexamples are collected (line 22). If there is at least one new counterexample, then SAT-based debugging is executed. After that the LMBA algorithm finishes.

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