By Sung Kyu Lim
This ebook offers readers with quite a few algorithms and software program instruments, devoted to the actual layout of through-silicon-via (TSV) dependent, three-d built-in circuits. It describes a number of “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs constructed with the instruments coated within the publication. This e-book also will characteristic sign-off point research of timing, energy, sign integrity, and thermal research for 3D IC designs. complete information of the comparable algorithms may be supplied in order that the readers can be capable not just to know the middle mechanics of the actual layout instruments, but additionally so as to reproduce and enhance upon the implications themselves. This e-book also will provide a number of design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) ideas which are thought of severe to the actual layout process.
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Additional info for Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
Cell 4 7 1 5 7 T2 6 6 T2 6 T2 5 3 T1 T1 2 2 During global placement (iteration N) TSV cell After global placement Assigned TSV cell in TSV site Fig. 9 TSV co-placement scheme: TSV insertion, 3D placement, and netlist generation number of TSVs to be inserted. We use only one TSV for a 3D net between two adjacent dies because we want to minimize the area overhead caused by TSV insertion. 2 TSV Insertion and Placement We study two ways to place TSVs in gate-level 3D IC designs: TSV co-placement (= irregular TSV location) and TSV site (= regular TSV location).
For detailed placement, we use the detailed placer of Cadence SoC Encounter . 5 3D Global Placement Algorithm 15 TSV site Netlist Net1: 1,2,3 Net2: 4,5,6,7 ... 4 4 5 T1 T2 T1 1 1 7 T3 T3 T4 3 2 Initial global placement 4 7 6 1 3 7 6 6 1 T4 3 5 T2 T1 T3 3 2 During global placement (iteration N) T4 2 After global placement 5 T2 T1 T3 7 6 4 5 T2 T4 Netlist Net1: 1,2,3,T3 Net2: 4,5,6,7,T2 ... 2 After TSV assignment Std. cell TSV cell Assigned TSV cell in TSV site Fig. 3 Routing After 3D placement, we dump the placement result into DEF files and generate a netlist file for each die.
In , the authors randomly place standard cells within the placement area and use forces to move the cells in three dimensions to reduce cell overlap and temperature. The cells are moved from continuous space to discrete space by the legalization of the placement result. The authors sort cells in the z-direction before placing them into the nearest layer. In , the authors transform a 2D placement result into 3D. The proposed transformations are based on folding and stacking a 2D design. After transformation, they use a graph-based layer assignment method to refine the 3D placement result by placing cells into multiple layers so that they reduce the number of TSVs and temperature.