Digital Design and Fabrication by Vojin G. Oklobdzija

By Vojin G. Oklobdzija

In keeping with super progress and new applied sciences within the semiconductor undefined, this quantity is geared up into 5, information-rich sections. electronic layout and Fabrication surveys the newest advances in laptop structure and layout in addition to the applied sciences used to fabricate and attempt them. that includes contributions from major specialists, the booklet additionally encompasses a new part on reminiscence and garage as well as a brand new bankruptcy on nonvolatile reminiscence applied sciences. constructing complex techniques, this sharply targeted e-book: * Describes new applied sciences that experience develop into using components for the digital undefined * contains new details on semiconductor reminiscence circuits, whose improvement top illustrates the outstanding development encountered through the fabrication and know-how region * encompasses a part devoted to matters with regards to approach strength intake * Describes reliability and testability of computers * Pinpoints developments and cutting-edge advances in fabrication and CMOS applied sciences * Describes functionality review measures, that are the base line from the user’s standpoint * Discusses layout options used to create smooth desktops, together with high-speed desktop mathematics and high-frequency layout, timing and clocking, and PLL and DLL layout

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2, when S ¼ 1, the NMOS acts like a closed switch, but if we connect VDD at the node A, at the node B instead of VDD we will get a voltage slightly less than VDD, for this reason we call this sigal a weak 1. But when VSS is connected at node A of the NMOS, at node B we get a strong ground and we call this signal a strong 0. Again, for the PMOS transistor, the complement is true. For the PMOS, when the gate signal S ¼ 0, if we connect VDD at the node A, we get a strong 1 at node B, and if we connect VSS at the node A, we get a weak 0 at node B.

Iwai, ‘‘Silicided silicon-sidewall source and drain (S4D) structure for high-performance 75-nm gate length p-MOSFETs,’’ Symp. , pp. 11–12, 1995. 10. T. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, H. Okano, I. Katakabe, H. Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, and H. Iwai, ‘‘A NiSi salicide technology for advanced logic devices,’’ IEDM Tech. , pp. 653–656, December, 1991. 11. Semiconductor Industry Association, ‘‘National Technology Roadmap for Semiconductors,’’ 1994, 1997 editions. 12.

593–596, 1994. 6. C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, and B. 025 mm MOSFET,’’ Symp. , pp. 33–34, 1993. 7. T. Ohguro, K. Yamada, N. Sugiyama, K. Usuda, Y. Akasaka, T. Yoshitomi, C. Fiegna, M. Ono, M. Saito, and H. Iwai, ‘‘Tenth micron P-MOSFET’s with ultra-thin epitaxial channel layer grown by ultra-high vacuum CVD,’’ IEDM Tech. , pp. 433–436, December, 1993. 8. T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. S. Momose, and H. 1 mm epitaxial Si channel n-MOSFETs grown by UHV-CVD,’’ Symp.

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