Security Aspects in Information Technology: First by Sanjay Burman (auth.), Marc Joye, Debdeep Mukhopadhyay,

By Sanjay Burman (auth.), Marc Joye, Debdeep Mukhopadhyay, Michael Tunstall (eds.)

This e-book constitutes the refereed lawsuits of the 1st overseas convention on protection elements in info expertise, High-Performance Computing and Networking held in Haldia, India, in October 2011. The 14 complete papers awarded including the abstracts of two invited lectures have been conscientiously reviewed and chosen from 112 sumbissions. The papers deal with all present elements in cryptography, protection features in excessive functionality computing and in networks in addition. The papers are divided in topical sections on embedded protection; electronic rights administration; cryptographic protocols; cryptanalysis/side channel assaults; and cipher primitives.

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Security Aspects in Information Technology: First International Conference, InfoSecHiComNet 2011, Haldia, India, October 19-22, 2011. Proceedings

This ebook constitutes the refereed lawsuits of the 1st overseas convention on safety facets in details expertise, High-Performance Computing and Networking held in Haldia, India, in October 2011. The 14 complete papers offered including the abstracts of two invited lectures have been rigorously reviewed and chosen from 112 sumbissions.

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Example text

The line through T and P is l(x, y) = (X2 (Y2 Z13 − Y1 ) − Y2 Z3 ) − (Y2 Z13 − Y1 )x + Z3 · y. During the addition step of Miller algorithm we compute the above operations in parallel on both cores. There are limited independent operations in this step. Therefore, there are scopes for optimizing the scheduling of operations on Fp arithmetic units for reducing the additional registers and related wiring. The respective scheduling is shown here. 1. 2. 3. 4. 5. 6. 7. 8. 9. t0 ← Y2 · Z1 , t0 ← (Z1 )2 t0 ← t1 · t0 , t1 ← t1 · X2 t4 ← t1 + X1 , t0 ← t0 − Y1 , t5 ← t1 − X1 t3 ← (t0 )2 , Z3 ← t5 · Z1 , t7 ← (t5 )2 ; l10 ← t0 · x0 , l11 ← t0 · x1 t2 ← t7 · X1 , t4 ← t4 · t7 , t5 ← t5 · t7 ; t10 ← t0 · X2 X3 ← t3 − t4 t2 ← t2 − X3 t2 ← t2 · t0 , t4 ← Y2 · Z3 , t5 ← t5 · Y1 ; l20 ← Z3 · y0 , l21 ← Z3 · y1 Y3 ← t2 − t5 ; l0 ← t10 − t4 In the above scheduling, the nonlinear operations (multiplication and squaring) in Fp are performed in steps 1, 2, 4, 5, and 8.

Next, we can obtain the value of y-coordinate of the secret point SID by solving the curve equation. 1 Mounting the DPA on FPGA Platform We perform the actual DPA attack on aforementioned pairing cryptoprocessor (or PCP). The PCP is implemented on a customized FPGA board for power analysis. We put an one ohm resistor between the VCCint pin of the FPGA chip and the on board voltage regulator. We measure the current drawn through that resistor during pairing computation by a current probe. The specification of the probe is Tektronix current probe (serial number B014316).

Implementing Cryptographic Pairings over Barreto-Naehrig Curves. , Okamoto, T. ) Pairing 2007. LNCS, vol. 4575, pp. 197–207. Springer, Heidelberg (2007) 17. : On the final exponentiation for calculating pairings on ordinary elliptic curves. , Waters, B. ) Pairing 2009. LNCS, vol. 5671, pp. 78–88. Springer, Heidelberg (2009) 18. : High speed flexible pairing cryptoprocessor on FPGA platform. , Otsuka, A. ) Pairing 2010. LNCS, vol. 6487, pp. 450–466. Springer, Heidelberg (2010) 19. : Identity-Based Encryption from the Weil Pairing.

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